A known solid-state imager of this kind is shown in FIG. 1, where an N-type doped region 17, or a P-well, is formed on an N-type silicon substrate 16. This imager has a sensor portion 2 having a charge storage layer 13 consisting of an N.sup.+ -type doped region. A positive hole storage region 12 consisting of a P.sup.+ -type doped region is formed on the charge storage layer 13. This is known as a hole accumulation diode (HAD) sensor structure.
An overflow control gate (OFCG) 4 consisting of an N-type doped region is formed adjacent to the sensor portion 2. An overflow drain (OFD) 8 consisting of an N.sup.+ -type doped region is formed adjacent to the overflow control gate 4.
An insulating layer (not shown) is formed on the overflow control gate 4. A gate electrode 15 made of polysilicon is formed on the insulating layer. A given DC voltage V.sub.G is applied to the gate electrode 15 to create a potential barrier.
If electric charge is accumulated in the sensor portion 2 by photoelectric conversion, that portion of the accumulated charge which exceeds the potential barrier of the overflow control gate 4 flows out into the overflow drain 8 and is then expelled through the drain 8.
The output voltage-incident light quantity characteristic of the solid-state imager having the above-described overflow drain structure is shown in FIG. 2. As can be seen from this, the characteristic exhibits a logarithmic property after an overflow point has been exceeded.
In the conventional solid-state imager having this horizontal overflow drain structure, a potential barrier is created in the overflow control gate 4 by providing the gate electrode 15 and applying a DC voltage V.sub.G to this gate electrode.
Especially, in the solid-state imager having the sensor portion 2 of the HAD sensor structure, when the positive hole storage layer 12 is formed, the gate electrode 15 on the overflow control gate 4 is used as a mask, and ions are injected such that the positive hole storage layer 12 is formed on the overflow control gate 4 by self-aligning techniques, as shown in FIG. 3.
However, the P.sup.+ -type impurity which is implanted, using the gate electrode 15 as a mask, is diffused in a thermal diffusion step or the like after the ion implantation step. Consequently, the impurity gets under the gate electrode 15, as shown in FIG. 3.
Thus, the positive storage layer 12 is clamped at ground level and acts as a virtual electrode. As shown in the potential diagram of FIG. 4, a barrier is created at an edge of the overflow control gate 4 where a P.sup.+ -type impurity has been diffused. As a result, an unwanted potential barrier is produced.
This unwanted potential barrier is varied, depending on the state of the polysilicon forming the gate electrode 15, on the manner in which the P.sup.+ -type impurity has been diffused, and on other factors. This produces variations among states of elements. In this way, the presence of the unwanted potential barrier makes it difficult to control the amount of overflow.